Tunable RF Notch Filters for Blocker Suppression

Periodically time-variant passive 8-path notch filters are demonstrated in 65nm CMOS technology, with a notch frequency tunable from 100MHz to 1.2GHz with a clock signal. In a 50Ω environment, filter insertion loss in the pass band is 1.4-2.8dB, while the rejection at the notch frequency is >20dB. Given their P1dB> +2dBm and IIP3> +17dBm, the filters can protect radio receivers from blocking over a wide tuning range. Text The huge growth of the number of wireless devices makes wireless coexistence an increasingly relevant issue. If radios operate in close proximity, blockers as strong as 0dBm may occur, driving almost any receiver in compression (note that 0dBm in 50Ω corresponds to a pk-pk voltage of half a 1.2V supply). Thus RF blocker filtering is highly wanted. However, fixed filters are undesired when aiming for multi-band, software defined or cognitive radio transceivers. Passive LC filters show limited Q and tunability. Recently frequency translated filtering has been proposed as a potential solution direction for high Q filtering [1-5]. In [1,2] we showed that by applying the “N-path concept” 2 [6], more than a decade of center frequency range with good linearity, compression point (P1dB>0dBm, IIP3 >14dBm) and low noise is feasible for a bandpass (BP) filter. In [3] a notch filter with a combination of active and passive mixers is applied in a feedforward path realizing a BP filter. Moreover in [5] the low input impedance of a transimpedance amplifier with feedback is upconverted to create a notch filter at low frequencies (80MHz) suppressing TX leakage in an FDD system. In this work we explore the possibility to realize a notch filter applying the N-path concept at RF frequencies and in a completely passive way. A single-ended (SE) and a differential 8-path notch filter with passive frequency mixing are presented. The filters are power-matched in the input and output in the passband and provide a low insertion loss, high compression point and also low noise property, thus they can be utilized in front of a receiver to provide rejection of high power blockers with a large frequency tuning range. A block diagram of an N-path notch filter is illustrated in Fig. 4.2.1. The input signal is downconverted, high-pass filtered and then upconverted to the same frequency band as the input experiencing a notch filter at the LO frequency. A simple form of a SE notch filter is illustrated in Fig. 4.2.1. Mixers are realized by switches driven by N multiphase clocks with a duty cycle of 1/N and the high-pass filter with a simple RC network. The resistance in the high pass filters is shared as RL. Moreover the upconverting mixer is simply implemented with the wired OR connection at the output node. A typical transfer curve of the notch filter is also illustrated in Fig. 4.2.1 representing the rejection at the switching frequency (fs) and its harmonics. As we showed in [2] the multipath switched-capacitor in Fig. 4.2.1 for the frequencies close to fs can be modeled as a parallel RLC tank circuit with a resonance at fs. In Fig. 4.2.1, Rp and Cp values are constant for a given number of paths but the inductor varies with fs. Note that a fixed RC value in a tank circuit implies a constant notch bandwidth. According to the expression of RP in Fig. 4.2.1, increasing of N will increase RP, and for an 8-path notch filter it reduces to: Rp≈19(Rs+RL) rendering 26dB rejection at fs if Rs=RL. Thus the amount of rejection is solely defined by N in an ideal N-path notch filter. The insertion loss in the passband is a function of the conversion gain of the mixers and increasing the number of paths will 3 reduce it (≈0.1dB for N=8). Still the switch resistance and parasitic capacitances might degrade the insertion loss in a real implementation. Similar to the N-path BP filter in [2] harmonic mixing might happen with (N-1) and (N+1) harmonics of fs. Therefore increasing the number of paths not only increase the amount of rejection at fs but also moves the folding-back components further away. To avoid harmful components, a time-invariant prefilter may be required as for all N-path filters. A prototype including a SE and a differential notch filter is implemented in 65nm CMOS technology (see Fig. 4.2.2 and 4.2.7). The circuit operates directly in a 50Ω system. In the differential architecture the notch is suppressed at the even harmonics of fs resulting in a wider passband. The second mixer in Fig. 4.2.1 (top left) is implemented by the second set of switches in the differential filter, exploiting the differential nature of the signals. Therefore 32 switches are required for an 8-path architecture. The harmonic folding characteristic and the amount of rejection in an ideal differential notch filter is expected to be similar to the SE version. The switches are realized by low threshold NMOS transistors and the capacitors with MIM technology. Large switch sizes (W/L=100u/65nm) are used resulting in switch resistance of 6Ω when driven by a swing of 0.9V (the DC voltage on the Source/Drains of the switches is set to 300mV to avoid reliability issues at high input swings). Larger switch would increase the insertion loss at high frequencies due to the parasitic capacitance and would require higher digital power drive. In the SE filter C1=7pF is chosen in each path targeting to suppress a 6MHz width blockers (e.g. TV channels in the cognitive radio or TV tuner applications). In the differential architecture two capacitors are in series and in order to get the same RC product as the SE version we have doubled the capacitor value (C2=14pF). For each filter, a divide-by-8 ring counter is implemented to provide a proper phase balance. The input frequency range of the clock divider is 0.8-9.6GHz. A PLL might be required to generate the input clock for the divider which is provided externally in this design. The generated phases in the divider are buffered and fed to the switches. Measurement results of the SE notch filter are shown in Fig. 4.2.3 for fs at 500MHz. The amount of rejection is limited to 22dB at fs due to the charge injection in the 4 switches. S21 renders 1.4-2.5dB insertion loss in the passband with an S11 <-10dB. Measured passband NF is 1.2-2.8dB which is roughly the same as loss. According to the simulation by applying a blocker of -5dBm at fs, the NF in the passband degrades by 1dB (due to the noise floor of our signal generator we didn’t manage to measure this). The measured IIP3 is better than +18dBm and P1dB is between 2-6dBm. P1dB in the passband is measured as -3dBm when a blocker with a power of 0dBm is applied at fs. Measurement results for the differential notch filter is presented in Fig. 4.2.4. As we expect there is no rejection in the second harmonic. Increasing of noise figure around the second harmonic is due to the leakage of the second harmonic of the clock. The tunability of the filter is illustrated in Fig. 4.2.5, showing S21 of the SE filter for fs=0.1-1.2GHz. The differential filter shows the same behavior. The group delay of the SE filter is measured and shown in Fig. 4.2.5 and compared to the prediction by the RLC model in Fig. 4.2.1. Similar to a passive tank circuit the group delay becomes flat in the passband representing a linear phase operation. In order to check the effect of the phase imbalance and mismatch on the performance of the filter we have measured the harmonic mixing effect in 10 samples for 3 switching frequencies in the SE notch filter. Fig. 4.2.5 illustrates the worst-case numbers of harmonic mixing in the passband. The key measured parameters of both filters are compared with two Q-enhanced notch filters [7,8]. Our method provides a higher dynamic range and is more robust to large blockers and PVT variations than the Q-enhancement technique. Moreover the die area is much smaller, especially at the low GHz bands and finally our approach has a much larger relative tuning range, only determined by a clock signal. Acknowledgment: This research is supported by STW. We thank STMicroelectronics for silicon donation and CMP for their assistance. Also thanks go to G. Wienk and H. de Vries.